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| INTEGRATED CIRCUITS DATA SHEET UDA1325 Universal Serial Bus (USB) CODEC Preliminary specification File under Integrated Circuits, IC01 1999 May 10 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 FEATURES General * High Quality USB-compliant Audio/HID device * Supports 12 Mbits/s serial data transmission * Fully USB Plug and Play operation * Supports `Bus-powered' and `Self-powered' operation * 3.3 V power supply * Low power consumption with optional efficient power control * On-chip clock oscillator, only an external crystal is required. Audio playback channel * One isochronous output endpoint * Supports multiple audio data formats (8, 16 and 24 bits) * Adaptive sample frequency support from 5 to 55 kHz * One master 20-bit I2S digital stereo playback output, I2S and LSB justified serial formats * One slave 20-bit I2S digital stereo playback input, I2S and LSB justified serial formats * Selectable volume control for left and right channel * Soft mute control * Digital bass and treble tone control * Selectable on-chip digital de-emphasis * Low total harmonic distortion (typical 90 dB) * High signal-to-noise ratio (typical 95 dB) * One stereo Line output. Audio recording channel * One isochronous input endpoint * Supports multiple audio data formats (8, 16 and 24 bits) * Twelve selectable sample rates (4, 8, 16 or 32 kHz; 5.5125, 11.025, 22.05 or 44.1 kHz; 6, 12, 24 or 48 kHz) via analog PLL (APLL). * Selectable sample rate between 5 to 55 kHz via a second oscillator (optional) * One slave 20-bit I2S digital stereo recording input, I2S and LSB justified serial formats * Programmable Gain Amplifier for left and right channel * Low total harmonic distortion (typical 85 dB) * High signal-to-noise ratio (typical 90 dB) * One stereo Line/Microphone input. USB endpoints * 2 control endpoints * 2 interrupt endpoints * 1 isochronous data sink endpoint * 1 isochronous data source endpoint. Document references * "USB Specification" * "USB Device Class Definition for Audio Devices" * "Device Class Definition for Human Interface Devices (HID)" * "USB HID Usage Table". * "USB Common Class Specification". 1999 May 10 2 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC APPLICATIONS * USB monitors * USB speakers * USB microphones * USB headsets * USB telephone/answering machines * USB links in consumer audio devices. GENERAL DESCRIPTION The UDA1325 is a single chip stereo USB codec incorporating bitstream converters designed for implementation in USB-compliant audio peripherals and multimedia audio applications. It contains a USB interface, an embedded microcontroller, an Analog-to-Digital Interface (ADIF) and an Asynchronous Digital-to-Analog Converter (ADAC). The USB interface consists of an analog front-end and a USB processor. The analog front-end transforms the differential USB data into a digital data stream. The USB processor buffers the incoming and outgoing data from the analog front-end and handles all low-level USB protocols. The USB processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information and audio information. The control information is made accessible to the microcontroller. At playback, the audio information becomes available at the digital I2S output of the digital I/O module or is fed directly to the ADAC. At recording, the audio information is delivered by the ADIF or by the digital I2S input of the I2S-bus interface. UDA1325 All I2S inputs and I2S outputs support standard I2S-bus format and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. Via the digital I/O module with its I2S input and output, an external DSP can be used for adding extra sound processing features for the audio playback channel. The microcontroller is responsible for handling the high-level USB protocols, translating the incoming control requests and managing the user interface via general purpose pins and an I2C-bus. The ADAC enables the wide and continuous range of playback sampling frequencies. By means of a Sample Frequency Generator (SFG), the ADAC is able to reconstruct the average sample frequency from the incoming audio samples. The ADAC also performs the playback sound processing. The ADAC consists of a FIFO, an unique audio feature processing DSP, the SFG, digital filters, a variable hold register, a Noise Shaper (NS) and a Filter Stream DAC (FSDAC) with line output drivers. The audio information is applied to the ADAC via the USB processor or via the digital I2S input of the digital I/O module. The ADIF consists of an Programmable Gain Amplifier (PGA), an Analog-to-Digital Converter (ADC) and a Decimator Filter (DF). An Analog Phase Lock Loop (APLL) or oscillator is used for creating the clock signal of the ADIF. The clock frequency for the ADIF can be controlled via the microcontroller. Several clock frequencies are possible for sampling the analog input signal at different sampling rates. The wide dynamic range of the bitstream conversion technique used in the UDA1325 for both the playback and recording channel guarantees a high audio sound quality. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1325PS UDA1325H SDIP42 QFP64 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT270-1 SOT319-2 1999 May 10 3 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC QUICK REFERENCE DATA SYMBOL Supplies VDDE VDDI IDD(tot) IDD(tot)(ps) supply voltage periphery supply voltage core total supply current total supply current in power-saving note 1 mode 4.75 3.0 - - 5.0 3.3 60 360 PARAMETER CONDITIONS MIN. TYP. UDA1325 MAX. UNIT 5.25 3.6 tbf - V V mA A Dynamic performance DAC (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; RL = 5 k fi = 1 kHz (0 dB) fi = 1 kHz (-60 dB) S/N Vo(FS)(rms) signal-to-noise ratio at bipolar zero full-scale output voltage (RMS value) - - - - A-weighted at code 0000H 90 VDD = 3.3 V - -90 0.0032 -30 3.2 95 0.66 -80 0.01 -20 10 - - dB % dB % dBA V Dynamic performance PGA and ADC (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; PGA gain = 0 dB fi = 1 kHz; (0 dB); Vi = 1.0 V (RMS) fi = 1 kHz (-60 dB) S/N signal-to-noise ratio Vi = 0.0 V - - - - 90 General characteristics fi(s) Tamb Note 1. Exclusive the IDDE current which depends on the components connected to the I/O pins. audio input sample frequency operating ambient temperature 5 0 - 25 55 70 kHz C -85 0.0056 -30 3.2 95 -80 0.01 -20 10.0 - dB % dB % dBA 1999 May 10 4 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC BLOCK DIAGRAM UDA1325 handbook, full pagewidth CLK 27 VSSX XTAL1b XTAL2b VDDX VDDA3 XTAL2a XTAL1a VSSA3 24 (19) 25 (20) 26 (21) 28 (22) 52 (39) 53 (40) 54 (41) 55 (42) OSC ADC ANALOG PLL USB-PROCESSOR OSC 48 MHz TIMING ANALOG FRONT-END D+ 8 (9) D- 6 (8) P0.7 to P0.0 7, 5, 3, 64, 62, 60, 58, 56 P2.0 to P2.7 14, 16, 18, 20, 22, 23, 29, 30 (10) 9 (11) 10 (12) 11 (13) 12 (23) 32 (24) 33 (29) 38 (30) 39 (33) 42 (35) 44 VDDI VSSI VSSE VDDE VDDO VSSO VDDA1 VSSA1 VDDA2 VSSA2 GP2/DO GP3/WSO GP4/BCKO GP1/DI GP0/BCKI GP5/WSI 63 (4) 1 (5) 2 (6) 13 (14) 17 (16) 15 (15) DIGITAL I/O (17) 19 MICROCONTROLLER (18) 21 SCL SDA PSEN 31 MUX FIFO DA WS BCK 57 (1) 59 (2) 61 (3) I2S-BUS INTERFACE DECIMATOR FILTER SAMPLE FREQUENCY GENERATOR AUDIO FEATURE PROCESSING DSP UPSAMPLE FILTERS TEST CONTROL BLOCK VARIABLE HOLD REGISTER (7) 4 (26) 35 (27) 36 SHTCB TC RTCB EA ALE 48 50 VINL 43 (34) PGA LEFT ADC 3rd-ORDER NOISE SHAPER UDA1325 VINR 47 (36) PGA RIGHT ADC LEFT DAC - + + (25) 34 VOUTL (28) 37 VOUTR REFERENCE VOLTAGE VRN VRP 49 (37) 51 (38) RIGHT DAC - 45, 46 n.c. 41 (32) Vref(AD) 40 (31) Vref(DA) MGM108 The pin numbers given in parenthesis refer to the SDIP42 version. Fig.1 Block diagram (QFP64 package). 1999 May 10 5 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC PINNING SYMBOL GP3/WSO GP4/BCKO P0.5 SHTCB P0.6 D- P0.7 D+ VDDI VSSI VSSE VDDE GP1/DI P2.0 GP5/WSI P2.1 GP0/BCKI P2.2 SCL P2.3 SDA P2.4 P2.5 VSSX XTAL1b XTAL2b CLK VDDX P2.6 P2.7 PSEN VDDO VSSO VOUTL TC RTCB VOUTR PIN QFP64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PIN SDIP42 5 6 - 7 - 8 - 9 10 11 12 13 14 - 15 - 16 - 17 - 18 - - 19 20 21 - 22 - - - 23 24 25 26 27 28 I/O I/O I/O I/O I I/O I/O I/O I/O - - - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I O O - I/O I/O I/O - - O I I O DESCRIPTION general purpose pin 3 or word select output general purpose pin 4 or bit clock output Port 0.5 of the microcontroller shift clock of the test control block (active HIGH) Port 0.6 of the microcontroller UDA1325 negative data line of the differential data bus, conforms to the USB standard Port 0.7 of the microcontroller positive data line of the differential data bus, conforms to the USB standard digital supply voltage for core digital ground for core digital ground for I/O pads digital supply voltage for I/O pads general purpose pin 1 or data input Port 2.0 of the microcontroller general purpose pin 5 or word select input Port 2.1 of the microcontroller general purpose pin 0 or bit clock input Port 2.2 of the microcontroller serial clock line I2C-bus Port 2.3 of the microcontroller serial data line I2C-bus Port 2.4 of the microcontroller Port 2.5 of the microcontroller crystal oscillator ground (48 MHz) crystal input (analog; 48 MHz) crystal output (analog; 48 MHz) 48 MHz clock output signal supply crystal oscillator (48 MHz) Port 2.6 of the microcontroller Port 2.7 of the microcontroller program store enable (active LOW) supply voltage for operational amplifier operational amplifier ground voltage output left channel test control input (active HIGH) asynchronous reset input of the test control block (active HIGH) voltage output right channel 1999 May 10 6 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 SYMBOL VDDA1 VSSA1 Vref(DA) Vref(AD) VDDA2 VINL VSSA2 n.c. n.c. VINR EA VRN ALE VRP VDDA3 XTAL2a XTAL1a VSSA3 P0.0 DA P0.1 WS P0.2 BCK P0.3 GP2/DO P0.4 PIN QFP64 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PIN SDIP42 29 30 31 32 33 34 35 - - 36 - 37 - 38 39 40 41 42 - 1 - 2 - 3 - 4 - I/O - - O O - I - - - I - I - I - O I - I/O I I/O I I/O I I/O I/O I/O analog supply voltage 1 analog ground 1 DESCRIPTION reference voltage output DAC reference voltage output ADC analog supply voltage 2 input signal left channel PGA analog ground 2 not connected not connected input signal right channel PGA external access (active LOW) negative reference input voltage ADC address latch enable (active HIGH) positive reference input voltage ADC supply voltage for crystal oscillator and analog PLL crystal output (analog; ADC) crystal input (analog; ADC) crystal oscillator and analog PLL ground Port 0.0 of the microcontroller data Input (digital) Port 0.1 of the microcontroller word select Input (digital) Port 0.2 of the microcontroller bit clock Input (digital) Port 0.3 of the microcontroller general purpose pin 2 or data output Port 0.4 of the microcontroller 1999 May 10 7 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 63 GP2/DO 54 XTAL1a 53 XTAL2a GP3/WSO 1 GP4/BCKO 2 P0.5 3 SHTCB 4 P0.6 5 D- 6 P0.7 7 D+ 8 VDDI 9 VSSI 10 VSSE 11 VDDE 12 GP1/DI 13 P2.0 14 GP5/WSI 15 P2.1 16 GP0/BCKI 17 P2.2 18 SCL 19 P2.3 20 SDA 21 P2.4 22 P2.5 23 VSSX 24 XTAL1b 25 XTAL2b 26 CLK 27 VDDX 28 P2.6 29 P2.7 30 PSEN 31 VDDO 32 55 VSSA3 handbook, full pagewidth 52 VDDA3 51 VRP 50 ALE 49 VRN 48 EA 47 VINR 46 n.c. 45 n.c. 44 VSSA2 43 VINL 42 VDDA2 41 Vref(AD) 40 Vref(DA) 39 VSSA1 38 VDDA1 37 VOUTR 36 RTCB 35 TC 34 VOUTL 33 VSSO MGL349 64 P0.4 62 P0.3 60 P0.2 58 P0.1 UDA1325H Fig.2 Pin configuration (QFP64 package). 1999 May 10 8 56 P0.0 61 BCK 59 WS 57 DA Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB) UDA1325 handbook, halfpage Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. DA WS BCK 1 2 3 4 5 6 7 8 9 42 VSSA3 41 XTAL1a 40 XTAL2a 39 VDDA3 38 VRP 37 VRN 36 VINR 35 VSSA2 34 VINL 33 VDDA2 The analog front-end The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s). The USB processor The USB processor forms the interface between the analog front-end, the ADIF, the ADAC and the microcontroller. The USB processor consists of: * A bit clock recovery circuit * The Philips Serial Interface Engine (PSIE) * The Memory Management Unit (MMU) * The Audio Sample Redistribution (ASR) module. Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using four times over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It translates the electrical USB signals into data bytes and control signals. Depending upon the USB device address and the USB endpoint address, the USB data is directed to the correct endpoint buffer. The data transfer could be of bulk, isochronous, control or interrupt type. The functions of the PSIE include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition and handshake evaluation/generation. The amount of bytes/packet on all endpoints is limited by the PSIE hardware to 8 bytes/packet, except for both isochronous endpoints (336 bytes/packet). 9 GP2/DO GP3/WSO GP4/BCKO SHTCB D- D+ VDDI 10 VSSI 11 VSSE 12 VDDE 13 GP1/DI 14 GP5/WSI 15 GP0/BCKI 16 SCL 17 SDA 18 VSSX 19 XTAL1b 20 XTAL2b 21 MGM106 UDA1325 32 Vref(AD) 31 Vref(DA) 30 VSSA1 29 VDDA1 28 VOUTR 27 RTCB 26 TC 25 VOUTL 24 VSSO 23 VDDO 22 VDDX Fig.3 Pin configuration (SDIP42 package). 1999 May 10 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Memory Management Unit (MMU) and integrated RAM The MMU and integrated RAM handle the temporary data storage of all USB packets that are received or sent over the bus. The MMU and integrated RAM handle the differences between data rate of the USB and the application allowing the microcontroller to read and write USB packets at its own speed. The audio data is transferred via an isochronous data sink endpoint or source endpoint and is stored directly into the RAM. Consequently, no handshaking mechanism is used. Audio Sample Redistribution (ASR) The ASR reads the audio samples from the MMU and integrated RAM and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to standard I2S-bus format or 16, 18 or 20 bits LSB-justified I2S-bus format. The ASR generates the bit clock output (BCKO) and the Word Select Output signal (WSO) of the I2S output. The 80C51 microcontroller The microcontroller receives the control information selected from the USB by the USB processor. It can be used for handling the high-level USB protocols and the user interfaces. The microcontroller does not handle the audio stream. The major task of the software process that is mapped upon the microcontroller, is to control the different modules of the UDA1325 in such a way that it behaves as a USB device. The embedded 80C51 microcontroller is compatible with the 80C51 family of microcontrollers described in the 80C51 family single-chip 8-bit microcontrollers of "Data Handbook IC20", which should be read in conjunction with this data sheet. The internal ROM size is 12 kbyte. The internal RAM size is 256 byte. A Watchdog Timer is not integrated. The Analog-to-Digital Interface (ADIF) UDA1325 The ADIF is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the USB interface. The ADIF consists of a stereo Programmable Gain Amplifier (PGA), a stereo Analog-to-Digital Converter (ADC) and Decimation Filters (DFs). The sample frequency of the ADC is determined by the ADC clock (see Section "The clock source of the analog-to-digital interface"). The user can also select a digital serial input instead of an analog input. In this event the sample frequency is determined by the continuous WS clock with a range between 5 to 55 kHz. Digital serial input is possible with four formats (I2S-bus, 16, 18 or 20 bits LSB-justified). Programmable Gain Amplifier circuit (PGA) This circuit can be used for a microphone or line input. The input audio signals can be amplified by seven different gains (-3 dB, 0 dB, 3 dB, 9 dB, 15 dB, 21 dB and 27 dB). The gain settings are given in Table 17. The Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1325 consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 128. Both ADCs can be switched off in power saving mode (left and right separate). The ADC clock is generated by the analog PLL or the ADC oscillator. The Decimation Filter (DF) The decimator filter converts the audio data from 128fs down to 1fs with a word width of 8, 16 or 24 bits. This data can be transmitted over the USB as mono or stereo in 1, 2 or 3 bytes/sample. The decimator filters are clocked by the ADC clock. 1999 May 10 10 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC The clock source of the analog-to-digital interface UDA1325 The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected. The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog PLL or from the ADC oscillator by a factor Q. Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1). By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC oscillator. Table 1 The analog PLL clock output frequencies APLL CLOCK FREQUENCY (MHz) 11.2896 8.1920 12.2880 11.2896 FCODE (1 AND 0) 00 01 10 11 The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of ADC clock signals allowing several different sample frequencies (see Table 2). Table 2 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source DIVIDE FACTOR Q 1 2 4 8 1 2 4 8 1 2 4 8 ADC CLOCK FREQUENCY (MHz) 4.096 2.048 1.024 0.512 (not supported) 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768 SAMPLE FREQUENCY (kHz) 32 16 8 4 (not supported) 44.1 22.05 11.025 5.5125 48 24 12 6 APLL CLOCK FREQUENCY (MHz) 8.1920 11.2896 12.2880 Table 3 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) Q(2) fosc/(2Q) SAMPLE FREQUENCY (kHz) fosc/(256Q)(3) OSCAD CLOCK FREQUENCY (MHz) fosc(1) Notes 1. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz. 2. The Q factor can be 1, 2, 4 or 8. 3. Sample frequencies below 5 kHz and above 55 kHz are not supported. 1999 May 10 11 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC The Asynchronous Digital-to-Analog Converter (ADAC) The ADAC receives audio data from the USB processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. After the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of: * A Sample Frequency Generator (SFG) * FIFO registers * An audio feature processing DSP * Two digital upsampling filters and a variable hold register * A digital Noise Shaper (NS) * A Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The Sample Frequency Generator (SFG) The SFG controls the timing signals for the asynchronous digital-to-analog conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the upsampling filters. The lock time of the digital PLL can be chosen (see Table 8). While the digital PLL is not in lock, the ADAC is muted. As soon as the digital PLL is in lock, the mute is released as described in Section "Soft mute control". First-In First-Out (FIFO) registers The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I/O input. The use of a FIFO (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal. The sound processing DSP A DSP processes the sound features. The control and mapping of the sound features is explained in Section "Controlling the playback features of the ADAC". Depending on the sampling rate (fs) the DSP knows four frequency domains in which the treble and bass are regulated. The domain is chosen automatically. Table 4 UDA1325 Frequency domains for audio processing by the DSP SAMPLE FREQUENCY (kHz) 5 to 12 12 to 25 25 to 40 40 to 55 DOMAIN 1 2 3 4 The upsampling filters and variable hold function After the audio feature processing DSP two upsampling filters and a variable hold function increase the oversampling rate to 128fs. The noise shaper A 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band. The Filter Stream DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. 1999 May 10 12 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC USB ENDPOINT DESCRIPTION The UDA1325 has following six endpoints: * USB control endpoint 0 * USB control endpoint 1 * USB status interrupt endpoint 1 * USB status interrupt endpoint 2 * Isochronous data sink endpoint * Isochronous data source endpoint. Table 5 Endpoint description ENDPOINT INDEX 0 1 1 2 3 4 5 2 3 4 5 6 7 interrupt interrupt isochronous out isochronous in control ENDPOINT TYPE control (default) DIRECTION out in out in in in out in 8 8 8 8 8 8 UDA1325 ENDPOINT NUMBER 0 MAX. PACKET SIZE (BYTES) 336 336 CONTROLLING THE PLAYBACK FEATURES Controlling the playback features of the ADAC The exchange of control information between the microcontroller and the ADAC is accomplished through a serial hardware interface comprising the following pins: L3_DATA: microcontroller interface data line L3_MODE: microcontroller interface mode line L3_CLK: microcontroller interface clock line. See also the description of Port 3 of the 80C51 microcontroller. Information transfer through the microcontroller bus is organized in accordance with the so-called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode. The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to program its sound processing features and other functional features. ADDRESS MODE The address mode is used to select a device (in this case the ADAC) for subsequent data transfer and to define the destination registers. The address mode is characterized by L3_MODE being LOW and a burst of 8 pulses on L3_CLK, accompanied by 8 data bits on L3_DATA. Data bits 0 and 1 indicate the type of the subsequent data transfer as shown in Table 6. 1999 May 10 13 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 6 Selection of data transfer type BIT1 0 0 1 1 BIT0 0 1 0 1 not used control registers not used DATA TRANSFER TYPE UDA1325 audio feature registers (volume left, volume right, bass and treble) Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its microcontroller interface logic. DATA TRANSFER MODE The selection preformed in the address mode remains active during subsequent data transfers, until the ADAC receives a new address command. The data transfer mode is characterized by L3_MODE being HIGH and a burst of 8 pulses on L3_CLK, accompanied by 8 data bits. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored in the ADAC after the eight bit of a byte has been received. The principle of a multibyte transfer is illustrated in the figure below. thalt ndbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGD018 PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data transfer type. This is performed in the address mode, bits 1 and 0 (see Table 6). The second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type. Data transfer type `audio feature registers' When the data transfer type `audio feature registers' is selected 4 audio feature registers can be selected depending on bits 7 and 6 of the data byte (see Table 7). 1999 May 10 14 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 7 BIT7 0 0 1 1 ADAC audio feature registers BIT6 0 1 0 1 BIT5 VR5 VL5 X X BIT4 VR4 VL4 BB4 TR4 BIT3 VR3 VL3 BB3 TR3 BIT2 VR2 VL2 BB2 TR2 BIT1 VR1 VL1 BB1 TR1 BIT0 VR0 VL0 BB0 TR0 volume left bass treble UDA1325 REGISTER volume right The sequence for controlling the ADAC audio feature registers via the L3-bus is given in the figure below. DATA_TRANSFER_TYPE (L3_MODE = LOW) L3_DATA 0 bit 0 LEFT VOLUME; TREBLE RIGHT VOLUME; BASS (L3_MODE = HIGH) L3_DATA X bit 0 X X X X X X X bit 7 0 1 0 DEVICE ADDRESS = $5 dbook, full pagewidth 1 0 0 0 bit 7 REGISTER ADDRESS L3_CLK MGS270 Data transfer type `control registers' When the data transfer type `control registers' is selected 2 general control registers can be selected depending on bit 7 of the data byte (see Table 7). The sequence for controlling the ADAC control registers via the L3-bus is given in the figure below. dbook, full pagewidth DATA_TRANSFER_TYPE (L3_MODE = LOW) L3_DATA 0 bit 0 1 1 0 DEVICE ADDRESS = $5 1 0 0 0 bit 7 DATA OF THE CONTROL REGISTER (L3_MODE = HIGH) L3_DATA X bit 0 X X X X X X REGISTER ADDRESS X bit 7 L3_CLK MGS269 1999 May 10 15 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 8 ADAC general control registers BIT 0 1 2 3 4 DESCRIPTION reset ADAC soft mute control synchronous/asynchronous channel manipulation de-emphasis 0 = not reset 1 = reset 0 = not muted 1 = mutes 0 = asynchronous 1 = synchronous 0 = L -> L, R -> R 1 = L -> R, R -> L 0 = de-emphasis off 1 = de-emphasis on 00 = flat mode 01 = min. mode 10 = min. mode 11 = max. mode 0 input format 00 = I2S-bus 01 = 16-bit LSB justified 10 = 18-bit LSB justified 11 = 20-bit LSB justified 00 = adaptive 01 = fix state 1 10 = fix state 2 11 = fix state 3 0 = adaptive 1 = fixed 00 = lock after 512 samples 01 = lock after 2048 samples 10 = lock after 4096 samples 11 = lock after 16348 samples 1 VALUE UDA1325 REGISTER Control register 0 COMMENT select 0 6 and 5 audio mode 7 Control register 1 selecting bit I2S-bus 1 and 0 serial 3 and 2 digital PLL mode select 00 4 digital PLL lock mode select 1 select 00 6 and 5 digital PLL lock speed 7 Soft mute control selecting bit When the mute (bit 1 of control register 0) is active for the playback channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. 1999 May 10 16 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Volume control UDA1325 The volume of the UDA1325 can be controlled from 0 dB down to -60 dB (in steps of 1 dB). Below -60 dB the audio signal is muted (- dB). The setting of 0 dB is always referenced to the maximum available volume setting. Independant volume control of the left and right channel is possible (balance control). Table 9 Volume settings right playback channel VR4 0 0 0 0 0 ... 1 1 1 1 VR3 0 0 0 0 0 ... 1 1 1 1 VR2 0 0 0 0 1 ... 1 1 1 1 VR1 0 0 1 1 0 ... 0 0 1 1 VR0 0 1 0 1 0 ... 0 1 0 1 VOLUME (dB) 0 0 -1 -2 -3 ... -59 -60 - - VR5 0 0 0 0 0 ... 1 1 1 1 Table 10 Volume settings left playback channel VL5 0 0 0 0 0 ... 1 1 1 1 VL4 0 0 0 0 0 ... 1 1 1 1 VL3 0 0 0 0 0 ... 1 1 1 1 VL2 0 0 0 0 1 ... 1 1 1 1 VL1 0 0 1 1 0 ... 0 0 1 1 VL0 0 1 0 1 0 ... 0 1 0 1 VOLUME (dB) 0 0 -1 -2 -3 ... -59 -60 - - 1999 May 10 17 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Treble control UDA1325 For the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode the audio is not influenced. In minimum and maximum mode, the treble range is from 0 to 6 dB in steps of 2 dB. The programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. Because of the exceptional amount of programmable gain, treble should be used with adequate prior attenuation, using volume control. Table 11 Treble settings TREBLE (dB) TR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 1 Bass control For the playback channel, bass can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode the audio is not influenced. In minimum mode the bass range is from 0 to approximately 14 dB in steps of 1.5 dB. In maximum mode, the bass range is from 0 to approximately 24 dB in steps of 2 dB. The programmable bass filters are implemented digitally and have a fixed corner frequency of 100 Hz for the minimum mode and 75 Hz for the maximum mode. Because of the exceptional amount of programmable gain, bass should be used with adequate prior attenuation, using volume control. TR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ... 1 TR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 TR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 1 TR0 FLAT SET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. SET 0 0 0 0 2 2 2 2 4 4 4 4 6 6 6 6 6 6 MAX. SET 0 0 0 0 2 2 2 2 4 4 4 4 6 6 6 6 6 6 1999 May 10 18 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 12 Bass boost settings UDA1325 BASS (dB) BB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 ... 1 De-emphasis De-emphasis is controlled by bit 4 of control register 0. The de-emphasis filter can be switched on or off. The digital de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz. De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples. BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 ... 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ... 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 1 BB0 FLAT SET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. SET 0 0 0 0 1.1 1.1 2.4 2.4 3.7 3.7 5.2 5.2 6.8 6.8 8.4 8.4 10.2 10.2 11.9 11.9 13.7 13.7 13.7 13.7 13.7 13.7 13.7 13.7 13.7 13.7 MAX. SET 0 0 0 0 1.7 1.7 3.6 3.6 5.4 5.4 7.4 7.4 9.4 9.4 11.3 11.3 13.3 13.3 15.2 15.2 17.3 17.3 19.2 19.2 21.2 21.2 23.2 23.2 23.2 23.2 1999 May 10 19 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Filter characteristics playback channel UDA1325 The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (fs = 44.1 kHz) handbook, full pagewidth -0 MGM110 -20 volume (dB) -40 -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 60 70 80 f (kHz) 90 100 Fig.4 Overall filter characteristics of the UDA1325. 1999 May 10 20 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC DSP extension port for enhanced playback audio processing UDA1325 An external DSP can be used for adding extra sound processing features via the I2S inputs and outputs of the digital I/O module. The UDA1325 supports the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O option the UDA1325 device acts as a master, controlling the BCKO and WSO signals. Using the 6-pin digital I/O option GP2, GP3 and GP4 are output pins (master) and GP0, GP1 and GP5 are input pins (slave). The period of the WSO signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WSO signal does not have a constant time period, but is jittery. The characteristic timing of the I2S-bus signals is illustrated in Figs 5 and 6. handbook, full pagewidth LEFT WS RIGHT th;WS ts;WS tr BCK tBCK(H) tf tBCK(L) Tcy ts;DAT th;DAT DATA LSB MSB MGK003 Fig.5 Timing of digital I/O input signals. 1999 May 10 21 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... book, full pagewidth 1999 May 10 WS 1 BCK DATA MSB B2 LSB MSB B2 2 LEFT 3 >=8 1 2 RIGHT 3 WS LEFT 16 BCK DATA MSB B2 B15 LSB 15 2 1 Philips Semiconductors Universal Serial Bus (USB) CODEC >=8 LSB MSB INPUT FORMAT I2S-BUS RIGHT 16 15 2 1 MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS 22 WS LEFT 18 17 16 15 2 1 18 RIGHT 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS WS 20 BCK DATA MSB B2 19 LEFT 18 17 16 15 2 1 20 19 18 RIGHT 17 16 15 2 1 B3 B4 B5 B6 B19 LSB MSB B2 B3 B4 B5 B6 B19 LSB MGK002 Preliminary specification LSB-JUSTIFIED FORMAT 20 BITS UDA1325 Fig.6 Input formats. Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC PORT DEFINITION 80C51 Port 1 Table 13 Port 1 of the 80C51 microcontroller 8 BIT PORT 1 BIT 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Port 3 Table 14 Port 3 of the 80C51 microcontroller 8 BIT PORT 3 BIT 3.0 3.1 FUNCTION ASR_error PSIE_MMU_SUSPEND LOW no error no suspend error suspend HIGH GP1 GP2 GP3 GP4 GP5 SCL SDA I2C-bus FUNCTION ADAC_error LOW no error error general purpose pins HIGH UDA1325 COMMENT COMMENT suspend input from USB interface during normal operation or input from restart circuit general purpose pin interrupt input from USB interface during normal operation or input from restart circuit 3.2 3.3 GP0 (INT0_N) PSIE_MMU_INT (INT1_N) 3.4 3.5 3.6 3.7 PSIE_MMU_READY L3_MODE L3_CLK L3_DATA 1999 May 10 23 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC MEMORY AND REGISTER SPACE 80C51 Overview registers Table 15 Register location and recommended values after Power-on reset ADDRESS 0800h 0801h 1000h 1001h 1002h 1003h 2000h 4000h 4001h PGA gain ADIF control clock shop settings reset control and APLL settings IO selection register power control ASR settings data register PSIE command register PSIE REGISTER RESET VALUE 09 5C 00 00 01 00 8B Interrupts ADDRESS Port registers 80h 90h A0h B0h P0 P1 P2 P3 REGISTER UDA1325 RESET VALUE FFh FFh FFh FFh I2C registers (SIO1 registers) D8h D9h DAh DBh S1CON S1STA S1DAT S1ADR 00h Table 16 Special function register location ADDRESS CPU registers 81h 82h 83h D0h E0h F0h SP DPL DPH PSW ACC B REGISTER RESET VALUE The UDA1325 supports up to five (of maximal 7) interrupt sources. Each interrupt source corresponds to an interrupt vector in the CPU program memory address space: Source 0: vector 0003h external interrupt 0 (INT0_N) Source 1: vector 000Bh Timer 0 interrupt Source 2: vector 0013h external interrupt 1 (INT1_N) Source 3: vector 001Bh Timer 1 interrupt Source 4: vector 0023h UART interrupt (not present) Source 5: vector 002Bh Timer 2 interrupt (not present) Source 6: vector 0033h I2C interrupt. INTERRUPT ENABLE REGISTER (IE) Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE. This register also contains a global interrupt enable bit (EA) which can be cleared to disable all interrupts at once. 7 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Power On Value EX0 (vector 0003h)) ET0 (vector 000Bh)) EX1 (vector 0013h) ET1 (vector 001Bh) ES0 (n.a.) ET2 (n.a.) ES1 (vector 0033h) EA Interrupt registers A8h B8h IE IP 00h 00h Timer 0 and Timer 1 registers 88h 89h 8Ah 8Bh 8Ch 8Dh T01CON T01MOD T0L T1L T0h T1h 00h 00h 00h 00h 00h 00h 0 PCON registers 87h PCON 00h 1999 May 10 24 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Internal registers Table 17 PGA gain registers ADDRESS 0800h REGISTER PGA gain register reserved PGA input selection PGA gain right channel COMMENTS BIT 7 6 X UDA1325 VALUE 0 (do not change it) 5, 4 and 3 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB 2, 1 and 0 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB PGA gain left channel Table 18 ADIF control registers ADDRESS 0801h REGISTER ADIF control register reserved number of bits per audio sample to be transmitted to the host COMMENTS BIT 7 6 and 5 X 00 = reserved 01 = 8 bits audio samples 10 = 16 bits audio samples 11 = 24 bits audio samples mono/stereo selection selection audio input recording channel selection high-pass filter of ADIF (DC-filter) I2S-bus input serial input format recording channel 4 3 2 1 and 0 0 = mono 1 = stereo 0 = digital serial audio input 1 = analog input 0 = high-pass filter off 1 = high-pass filter on 00 = I2S-bus 01 = 16-bit LSB justified 10 = 18-bit LSB justified 11 = 20-bit LSB justified VALUE 1999 May 10 25 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 19 Clock shop register ADDRESS 1000h REGISTER clock shop settings COMMENTS selection ADC clock source divide factor Q BIT 7 6 and 5 UDA1325 VALUE 0 = ADC clock from APLL 1 = ADC clock from OSCAD 00 = ADC clock divided-by-1 01 = ADC clock divided-by-2 10 = ADC clock divided-by-4 11 = ADC clock divided-by-8 clock ADAC clock 48 MHz internal clock recovered by PSIE ADC clock OSCAD oscillator 4 3 2 1 0 0 = enable 1 = disable 0 = enable 1 = disable 0 = enable 1 = disable 0 = enable 1 = disable 0 = power on 1 = power off Table 20 Reset control and APLL register ADDRESS 1001h REGISTER reset control and APLL settings COMMENTS fcode (1 and 0) clock frequency selection APLL BIT 7 and 6 VALUE 00 = 256 x 44.1 kHz 01 = 256 x 32 kHz 10 = 256 x 48 kHz 11 = 256 x 44.1 kHz X 0 = reset off 1 = reset on 0 = reset off 1 = reset on 0 = reset off 1 = reset on 0 = reset off 1 = reset on X reserved reset ADAC reset MMU reset digital I/O-interface reset ADIF reserved 5 4 3 2 1 0 1999 May 10 26 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 21 I/O selection register ADDRESS 1002h REGISTER I/O selection register COMMENTS microcontroller control on 48 MHz oscillator audio format BIT 7 UDA1325 VALUE 0 = UPC control disabled (48 MHz oscillator is enabled) 1 = UPC control enabled 00 = 4-pins I2S 01 = 6-pins I2S 10 = 3-pins I2S (only input) 11 = 3-pins I2S (only input) 0 = output 1 = input 0 = output 1 = input 0 = output 1 = input 0 = output 1 = input 0 = I2S usage 1 = general purpose usage 6 and 5 GP4 I/O if BIT0 = 1 GP3 I/O if BIT0 = 1 GP2 I/O if BIT0 = 1 GP1 I/O if BIT0 = 1 GP4 to GP1 function 4 3 2 1 0 Table 22 Power control register ADDRESS 1003h REGISTER power control register analog modules COMMENTS suspend input selection for P3.1 of the microcontroller BIT 7 VALUE 0 = suspend from USB interface connected to P3.1 during normal operation 1 = suspend from restart circuit connected to P3.1 (e.g. after power-down) 0 = interrupt from USB interface connected to P3.3 during normal operation 1 = interrupt from restart circuit connected to P3.3 (e.g. after power-down) 0 = power on 1 = power off 0 = power on 1 = power off 0 = power on 1 = power off 0 = power on 1 = power off 0 = power on 1 = power off 0 = power on 1 = power off interrupt input selection for P3.3 (INT1_N) of the microcontroller 6 power APLL power FSDAC power ADC left power ADC right power PGA left power PGA right 5 4 3 2 1 0 1999 May 10 27 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 23 ASR control register ADDRESS 2000h REGISTER ASR control register COMMENTS robust word clock serial I2S-bus output format digital I/O interface BIT 7 6 and 5 UDA1325 VALUE 0 = off (not recommended) 1 = on (recommended) 00 = I2S-bus 01 = 16-bit LSB justified 10 = 18-bit LSB justified 11 = 20-bit LSB justified phase inversion (on right mono output) bits per sample modi 4 3 and 2 0 = mono phase inversal off 1 = mono phase inversal on 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio mono or stereo operation ASR register start-up mode 1 0 0 = mono 1 = stereo 0 = stop (e.g. at alternate setting with bandwidth equal to zero) 1 = go START-UP BEHAVIOUR AND POWER MANAGEMENT Start-up of the UDA1325 After power-on (of VDDA1), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is created by using the internal resistor (2 x 50 k) divider for creating the reference voltage for the FSDAC in combination with the capacitor connected externally to the VREFDA pin. The FSDAC and the internal resistor divider are supplied by VDDA1 and VSSA1. The RC time can be calculated using R = 25000 and C = Cref. During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this initialisation, the user should prevent indicating the `connected' status to the USB-host. This can be done by forcing the DP-line LOW (i.e. via one of the GP pins). Power Management The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less than 500 A in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can be reduced by disabling all internal clocks and switching off all internal analog modules. Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a number of precautions must be taken! 1999 May 10 28 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC AT INITIALISATION TIME UDA1325 * Bit 7of the power control register (mux_ctrl_suspend) must be set to `1', in order to connect the CLK_ON of the USB processor with P3.1 of the microcontroller * Bit 6 of the power control register (mux_ctrl_int1) must be set to `0', in order to connect the PSIE_MMU_INT output pin of the USB processor with P3.3 (INT1_N) of the microcontroller * Bit 7of the I/O selection register must be set to `1', in order to enable the power-on control of the 48 MHz crystal oscillator automatically by the microcontroller. IN NORMAL OPERATION MODE In normal operation working mode, a suspend can be initiated by the falling edge of the CLK_ON output signal of the USB processor. This falling edge comes about 2 ms after the rising edge of the PSIE_MMU_SUSPEND output signal of the USB processor. At this moment, several actions should be taken by the microcontroller: * All analog modules of the UDA1325 must be switched off; this can be done by setting bits 5 to 0 of the power control register to `1' and bit 0 of the clock shop register to `1' * Bit 6 of the power control register (mux_ctrl_int1) must be set to `1', in order to awake from power-down by the CLK_ON signal of the USB processor * Put all GP pins in the high or low state (depending of how they are used in the UDA1325 application) * Put the microcontroller in Power-down mode. This can be done via the PCON register of the microcontroller. This results in an automatically switching off the 48 MHz crystal oscillator and with that all internal clocks (if they are enabled). On the rising edge of the CLK_ON output signal, the 48 MHz crystal oscillator will be switched on automatically and with that all internal clocks (if they are enabled). At the same time, a counter starts counting for 2048 clock cycles (170 s). This time is necessary for stabilising the 48 MHz clock of the 48 MHz crystal oscillator. When the counter reaches its end value (after 2048 cycles), a rising edge will be detected on the P3.3 (INT1_N) of the microcontroller. At this moment, following actions should be taken by the microcontroller: * The Power-down mode of the microcontroller must be switched off * Re-initialise all GP pins * All analog modules of the UDA1325 must be switched on; this can be done by setting bits 5 to 0 of the power control register to `0' and bit 0 of the clock shop register to `0' * Bit 6 of the power control register (mux_ctrl_int1) must be set to `0', in order to connect the PSIE_MMU_INT output pin of the USB processor again with P3.3 (INT1_N) of the microcontroller. The UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge of the CLK_ON signal of the USB processor. 1999 May 10 29 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC COMMAND SUMMARY COMMAND NAME Initialization commands Set address/enable Read address/enable Set endpoint enable Read endpoint enable Set mode Data flow commands Read interrupt register Select endpoint device control OUT control IN other endpoints Get endpoint status control OUT control IN other endpoints Set endpoint status control OUT control IN other endpoints Read buffer Write buffer Acknowledge setup Clear buffer Validate buffer General commands Read current frame number F5h selected endpoint selected endpoint selected endpoint selected endpoint selected endpoint F4h 00h 01h 00h + endpoint index 40h 41h 40h + endpoint index 40h 41h 40h + endpoint index F0h F0h F1h F2h FAh read 1 byte device device device device device D0h D0h D8h D8h F3h write 1 byte read 1 byte write 1 byte read 1 byte write 1 byte RECIPIENT CODING UDA1325 DATA PHASE read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte read 1 byte read 1 byte write 1 byte write 1 byte write 1 byte read n bytes write n bytes none none none read 1 or 2 bytes 1999 May 10 30 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC COMMAND DESCRIPTIONS Command procedure This chapter describes the commands that can be used by the microcontroller to control the USB processor. There are three basic types of commands: * Initialization commands * Data flow commands * General commands. A command is represented by an 8 bit code. It can be followed by one or more data write cycles or one or more read cycles or a combination. The PSIE_MMU_READY output connected to Port 3.4 of the microcontroller indicates that the previous action (command write, data read or data write) has completed. A new action can only be initiated if PSIE_MMU_READY is TRUE. The data is valid from the moment PSIE_MMU_READY becomes TRUE. The PSIE contains a number of interrupt registers, one for each endpoint. Every time a transition occurs, the interrupt flag for the involved endpoint is set. The PSIE_MMU_INT connected to Port 3.3 is an OR function of all interrupt registers. Initialization commands Initialization commands are used during the enumeration process of the USB network. They are used to set the USB assigned address, enable endpoints and select the configuration of the device. SET ADDRESS/ENABLE Command: D0h. Data: write 1 byte. The set address/enable command is used to set the USB assigned address and enable the function. The device always powers up disabled and should be enabled after a bus reset. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Power On Value Address Enable UDA1325 Table 24 BIT Address Enable READ ADDRESS/ENABLE Command: D0h. Data: read 1 byte. The read address/enable command is used to read the USB assigned address and the enable bit of the device. The format of the data phase is the same as for the set address/enable command. SET ENDPOINT ENABLE Command: D8h. Data: write 1 byte. The set endpoint enable command is used to set the enable bits for the non default endpoints. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 Power On Value Enable Reserved DESCRIPTION the value written becomes the device address a `1' enables this function If the enable bit is `1', the non default endpoints are enabled, if `0', the non default endpoints are disabled. The function then only responds to the default control endpoint. After bus reset, the enable bit is set to `0'. READ ENDPOINT ENABLE Command: D8h. Data: read 1 byte. The read endpoint enable command is used to read the enable bit for the non default endpoints of the function. The format of the data phase is the same as for the set endpoint enable command. SET MODE Command: F3h. Data: write 1 byte. 1999 May 10 31 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 An interrupt is also generated after a bus reset. When the interrupt register consists of all zeros, and an interrupt was generated, there was a bus reset. The interrupt is cleared when the interrupt register is read. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Power On Value Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 IN Endpoint 3 IN Endpoint 4 OUT Endpoint 5 IN 7 0 T 6 0 T 5 1 F 4 1 F 3 1 T 2 1 T 1 1 T 0 1 T Reset value Bus Reset IsoOut IsoIn IntIsoOut IntIsoIn ErrorDebugMode AlwaysPLLClock Reserved Reserved Reset value: gives the value of the bits after Power-on reset. Bus reset: a `F' indicates that the value of the bit is not changed during a bus reset. a `T' indicates that during a bus reset, the bit is reset to its reset value. Table 25 BIT IsoOut IsoIn IntIsoOut IntIsoIn ErrorDebugMode AlwaysPLLClock DESCRIPTION ISO out endpoint can be used ISO in endpoint can be used allow interrupt from ISO out endpoint allow interrupt from ISO in endpoint Setting chip in debug mode the PLL clock must keep on running SELECT ENDPOINT Command: 00h + endpoint index. Data: optional read 1 byte. The select endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read. Bit 0 is low if the buffer is empty and high if the buffer is full. There is one command for every endpoint. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 Power On Value Full/Empty Reserved GET ENDPOINT STATUS Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the host. Much of the data flow is initiated via the interrupt to the microcontroller. The microcontroller uses these commands to access the endpoint buffers and determine whether the endpoint buffers have valid data. READ INTERRUPT REGISTER Command: F4h. 7 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Power On Value Data Receive/Transmit Error Code Setup Packet Data 0/1 Packet Previous Status not Read Command: 40h + endpoint index. Data: read 1 byte. The get endpoint status command is followed by one data read that returns the status of the last transaction of the selected endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read. There is one command for every endpoint. Data: read 1 byte. 0 The read interrupt register command returns the value of the interrupt register. Every time a packet is received or transmitted, an interrupt will be generated and a flag specific to the physical endpoint will be set in the interrupt register. Reading the status of the endpoint will clear the flag. 1999 May 10 32 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Table 26 Error codes ERROR CODE 0000 0001 0010 0011 no error PID encoding error; bits 7 to 4 in the PID token are not the inversion of bits 3 to 0 PID unknown; PID encoding is valid, but PID does not exist unexpected packet; packet is not of the type expected (token, data or acknowledge), or SETUP token received on non-control endpoint token CRC error data CRC error time out error babble error unexpected end-of-packet sent or received NAK sent stall, a token was received, but the endpoint was stalled overflow error, the received data packet was larger then the buffer size of the selected endpoint sent empty packet (ISO only) bitstuff error error in sync wrong data PID READ BUFFER Command: F0h. Data: read n bytes (max. 10). 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 UDA1325 SET ENDPOINT STATUS RESULT Command: 40h + endpoint index. Data: write 1 byte. This command is used to stall or unstall an endpoint. Only the least significant bit has a meaning. When the stalled bit is equal to 1, the endpoint is stalled, when equal to 0, the endpoint is unstalled. There is one command for every endpoint. A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the contents of the packet. If the endpoint should stay in stalled state, the microcontroller should restall it. When a stalled endpoint is unstalled, it is also re-initialized. This means that its buffer is flushed and the next DATA PID that will be sent or expected (depending on the direction of the endpoint) is DATA0. 0100 0101 0110 0111 1000 1001 1010 1011 Power On Value Stalled Reserved 1100 1101 1110 1111 Table 27 BIT Data receive/transmit DESCRIPTION a `1' indicates data has been received or transmitted successfully see Table 26 a `1' indicates the last received packet had a SETUP token (this will always read `0' for IN buffers) a `1' indicates the last received packet had a DATA 1 PID a `1' indicates a second event occurred before the previous status was read The read buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1. The buffer pointer is not reset to the buffer start by the read buffer command. This means that reading a buffer can be interrupted by any other command (except for select endpoint). Error code Setup packet Data 0/1 packet Previous status not read 1999 May 10 33 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC The data in the buffer are organized as follows: Byte 0: transfer successful, number of data bytes (MSB) Byte 1: number of data bytes (LSB) Byte 2: data byte 0 Byte 3: data byte 1 Byte 4: data byte 2 Byte 5: data byte 3 Byte 6: data byte 4 Byte 7: data byte 5 Byte 8: data byte 6 Byte 9: data byte 7. Bytes 0 and 1 indicate the number of bytes in the buffer. Byte 0 is the Most Significant Byte (MSB). Byte 1 is the Least Significant Byte (LSB). Only bits 1 and 0 of byte 0 are used in the number of bytes indication. Bit 7 of byte 0 indicates if the transaction was successful (bit 7 is `1' if the transaction was successful). Bits 6 to 2 of byte 0 are reserved. WRITE BUFFER Command: F0h. Data: write n bytes (max. 10). The write buffer command is followed by a number of data writes, which load the endpoint buffer. After each write, the internal buffer pointer is incremented by 1. The buffer pointer is not reset to the buffer start by the write buffer command. This means that writing a buffer can be interrupted by any other command (except for select endpoint). The data must be organized in the same way as described in the read buffer command. Bits 7 to 2 of byte 0 are reserved and must be filled with zeros. ACKNOWLEDGE SETUP Command: F1h. Data: none. The arrival of a SETUP packet flushes the IN buffer and disables the validate buffer and clear buffer commands for both IN and OUT endpoints. The microcontroller needs to re-enable these commands by the acknowledge setup command. This ensures that the last SETUP packet stays in the buffer and no packet can be sent back to the host until the microcontroller has UDA1325 acknowledged explicitly that it has seen the SETUP packet. If the microcontroller is reading the data from a SETUP packet, and a new SETUP packet arrives, the device must accept this new SETUP packet. So the data, currently being read by the microcontroller, is overwritten with the new packet. On the arrival of the new packet, the commands validate buffer and clear buffer are disabled. If the microcontroller has finished reading the data from the buffer, it will try to clear the buffer. The device will ignore this command, so the new SETUP packet in the buffer is not cleared. The microcontroller will now detect the interrupt of the new SETUP packet and will start reading the new data in the buffer. A SETUP token can be followed by an IN token. After the SETUP token, the microcontroller will start filling the IN buffer. A SETUP token will clear the IN buffer. This avoids the following problem: after a SETUP token, the microcontroller fills the IN buffer. If the SETUP token is followed by a SETUP token and shortly followed by an IN token, the device will send the contents of the IN buffer to the host. The IN buffer was filled after the first SETUP token. That is why after a SETUP token the IN buffer is cleared. If the microcontroller is still filling the buffer when the second SETUP token arrives, the SETUP token will clear the IN buffer. If the microcontroller has filled the IN buffer, it will validate the buffer. So clearing the IN buffer on receiving a SETUP token is not enough. If a SETUP token is received, the device will also disable the validate buffer command for the IN buffer. If the microcontroller needs to fill the buffer after a SETUP token, the command acknowledge setup command must be sent to enable the validate buffer command. CLEAR BUFFER Command: F2h. Data: none. When a packet is received completely, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NACK to the host. When the microcontroller has read the data, it should free the buffer by the clear buffer command. When the buffer is cleared, new packets will be accepted. 1999 May 10 34 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC VALIDATE BUFFER Command: FAh. Data: none. When the microcontroller has written data into an IN buffer, it should set the buffer full flag by the validate buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. General commands READ CURRENT FRAME NUMBER Command: F5h. Data: read 1 or 2 bytes. This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number is returned least significant byte first. In case the user is only interested in the lower 8 bits of the frame number only the first byte needs to be read. I2C MASTER/SLAVE INTERFACE The module implements a master/slave interface with integrated shift register, shift timing generation and slave address recognition. It is compliant to the I2C-bus specification IC20/Jan92. I2C standard mode (100 kHz SCL) and fast mode (400 kHz) are supported. Low speed mode and extended 10 bit addressing are unsupported. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to VDDE via a pull-up resistor. The timing definition of the I2C-bus is given in Fig.7. Programmer's view For a detailed description of the I2C-bus protocol refer to Philips Integrated Circuits Data Handbook IC20, 8XC552. The programmer's view of the I2C library function is -with one exception- identical to that of the 8XC552 microcontroller. Only the bit rate frequency selection in S1CON and the handling of the Timer 1 overflow information deviates to accommodate 400 kHz operation. I2C I2C-bus S1CON register UDA1325 The CPU can read from and write to this 8-bit SFR. Two bits are effected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C-bus. The STO bit is also cleared when ENS1 = `0'. Reset initializes S1CON to 00h. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Power On Value CR0 CR1 AA SI STO STA ENS1 CR2 CR2, 1 AND 0 - THE CLOCK RATE BITS These three bits determine the serial clock frequency when SIO1 is in a master mode. The various serial rates are shown in Table 28. Table 28 Serial clock rates (SCL line) CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 I2C BIT FREQUENCY (kHz) 1200 600 400 300 150 100 75 3.9 ... 501 When the CR bits are `111', the maximum bit rate for the data transfer will be derived from the Timer 1 overflow rate divided by 2 (i.e. every time the Timer 1 overflows, the SCL signal will toggle). 1999 May 10 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 10 SDA t BUF t LOW tr tf t HD;STA t SP Philips Semiconductors Universal Serial Bus (USB) CODEC Fig.7 Definition of timing of the I2C-bus. handbook, full pagewidth 36 SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr MBC611 P Preliminary specification UDA1325 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL All digital I/Os VI/O IO Tj Tstg Tamb Ves DC input/output voltage range output current VDDE = 5.0 V -0.5 - - - - - 25 - - VDDE 4 PARAMETER CONDITIONS MIN. TYP. UDA1325 MAX. UNIT V mA C C C Temperature values junction temperature storage temperature operating ambient temperature 0 -55 0 -3000 -300 125 +150 70 Electrostatic handling electrostatic handling note 1 note 2 Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor through a 2.5 H series conductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) UDA1325PS UDA1325H RECOMMENDED OPERATING CONDITIONS SYMBOL VDDE VDD VI PARAMETER supply voltage periphery (I/O) supply voltage (core) DC input voltage range for D+ and D- for VINL and VINR for digital I/Os 0.0 - 0.0 - 0.5VDD - VDD - VDDE V V V 3.0 MIN. 4.75 5.0 3.3 TYP. MAX. 5.25 3.6 V V UNIT PARAMETER thermal resistance from junction to ambient in free air in free air 48 48 K/W K/W CONDITIONS VALUE UNIT +3000 +300 V V 1999 May 10 37 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC DC CHARACTERISTICS VDDE = 5.0 V; VDD = 3.3 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL Supplies VDDE VDDI VDDA1 VDDA2 VDDA3 VDDO VDDX IDDE IDDI IDDA1 IDDA2 IDDA3 IDDO IDDX Ptot Pps digital supply voltage periphery digital supply voltage core analog supply voltage 1 analog supply voltage 2 analog supply voltage 3 operational amplifier supply voltage crystal oscillator supply voltage digital supply current periphery digital supply current core analog supply current 1 analog supply current 2 analog supply current 3 operational amplifier supply current crystal oscillator supply current total power dissipation total power dissipation in power saving mode note 4 note 1 4.75 3.0 3.0 3.0 3.0 3.0 3.0 - - - - - - - - - 5.0 3.3 3.3 3.3 3.3 3.3 3.3 3.7 39.0 3.6 8.0 0.9 3.0 1.2 200 1.2 5.25 3.6 3.6 3.6 3.6 3.6 3.6 - - - - PARAMETER CONDITIONS MIN. TYP. UDA1325 MAX. UNIT V V V V V V V mA mA mA mA mA mA mA mW mW 9.0(2) - 13.0(3) - - Inputs/outputs D+ and D- VI VO(H) VO(L) ILO VI(diff) VCM(diff) VSE(R)(th) CIN VIL VIH ILI CI static DC input voltage static DC output voltage HIGH static DC output voltage LOW high impedance data line output leakage current differential input sensitivity differential common mode range single-ended receiver threshold voltage transceiver input capacitance pin to GND -0.5 RL = 15 k 2.8 connected to GND RL = 1.5 k connected to VDD - - 0.2 0.8 0.8 - - 0.7VDDE - - - - - - - - - - - - - - VDDI 3.6 0.3 10 - 2.5 2.0 20 V V V A V V V pF Digital input pins LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 0.3VDDE VDDE 1 5 V V A pF 1999 May 10 38 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 SYMBOL PGA and ADC Vref(AD) Vref(ADC)(pos) Vref(ADC)(neg) VI(PGA) RI(PGA) PARAMETER CONDITIONS - - - - - MIN. TYP. - - - - - MAX. UNIT reference voltage PGA and ADC positive reference voltage of the ADC negative reference voltage of the ADC DC input voltage VINL and VINR of the PGA DC input resistance at VINL and VINR of the PGA 0.5VDDA2 VDDA2 0.0 0.5VDDA2 12.5 V V V V k Filter stream DAC Vref(DA) VO(CM) RO(VOUT) RO(L) CO(L) Notes 1. This value depends strongly on the application. The specified value is the typical value obtained using the application diagram as illustrated in Fig.8. 2. At start-up of the OSCAD oscillator. 3. At start-up of the OSC48 oscillator. 4. Exclusive the IDDE current which depends on the components connected to the I/O pins. reference voltage DAC common mode output voltage output resistance at VOUTL and VOUTR output load resistance output load capacitance - - - 2.0 - 0.5VDDA1 0.5VDDA1 11 - - - - - - 50 V V k pF 1999 May 10 39 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC AC CHARACTERISTICS VDDE = 5.0 V; VDDI = 3.3 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - 12.00 1.0000 0.0 0.0 - - 0.0 0.0 - - TYP. UDA1325 MAX. UNIT Driver characteristics D+ and D- (full-speed mode) fo(s) tr tf trf(m) Vcr Ro(drive) fi(s) ffs(D) tfr(D) tJ1(diff) tJ2(diff) tW(EOP) tEOP(diff) tJR1 tJR2 tEOPR1 tEOPR2 audio sample output frequency rise time fall time rise/fall time matching (tr/tf) output signal crossover voltage driver output resistance steady-state drive CL = 50 pF CL = 50 pF 5 4 4 90 1.3 28 55 20 20 110 2.0 43 kHz ns ns % V Data source timings D+ and D- (full-speed mode) audio sample input frequency full speed data rate frame interval source differential jitter to next transition source differential jitter for paired transitions source end of packet width differential to end of packet transition skew receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions end of packet width at receiver must reject as end of packet end of packet width at receiver must accept as end of packet 5 11.97 0.9995 -3.5 -4.0 160 -2.0 -18.5 -9.0 40 82 55 12.03 1.0005 +3.5 +4.0 175 +5.0 +18.5 +9.0 - - kHz Mbits/s ms ns ns ns ns ns ns ns ns Serial input/output data timing fs fi(WS) tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS system clock frequency word selection input frequency rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time word selection set-up time word selection hold time - 5 - - 55 55 10 20 20 10 12 - - - - - - - - - - 55 20 20 - - - - - - MHz kHz ns ns ns ns ns ns ns ns 1999 May 10 40 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT SDA and SCL lines for 100 kHz I2C devices fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf CL(bus) fosc gm Ro Ci(XTAL1a) Ci(XTAL2a) Istart fosc gm Ro Ci(XTAL1b) Ci(XTAL2b) Istart SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line 0 4.7 4.0 4.7 4.0 4.7 4.0 5.0 250 - - - - - 12.8 0.6 4.5 4.1 3.7 - - - - - - - - - - - - 100 - - - - - - - - 1000 300 400 - - 30.2 2.3 5.2 5.0 13.0 kHz s s s s s s s ns ns ns pF Oscillator 1 (system clock) oscillator frequency duty factor transconductance output resistance parasitic input capacitance XTAL1a parasitic input capacitance XTAL2a start-up current 48 50 22.1 1.1 4.8 4.6 7.6 - 50 13.6 2.0 5.4 4.6 5.0 MHz % mS k pF pF mA Oscillator 2 (for ADC clock) oscillator frequency duty cycle transconductance output resistance parasitic input capacitance XTAL1b parasitic input capacitance XTAL2b start-up current 8.192 - 8.1 1.3 5.0 4.1 2.4 14.08 - 18.1 4.0 5.7 5.0 8.4 MHz % mA/V k pF pF mA 1999 May 10 41 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog PLL (for ADC clock) fclk(PLL) tstrt(PO) tsu(PO) PGA and ADC Vi(FS)(rms) full-scale input voltage (RMS value) PGA gain = -3 dB - PGA gain = 0 dB PGA gain = 3 dB PGA gain = 9 dB - - - 1414(3) 1000 708 355 178 89 44 - - - - - - - - 20 mV mV mV mV mV mV mV pF PLL clock frequency duty factor start-up time after power-on 8.1920 - - 25Cref(2) 11.2896 50 - - 12.2880 - 10 - MHz % ms Power-on reset power-on set-up-time note 1 ms PGA gain = 15 dB - PGA gain = 21 dB - PGA gain = 27 dB - Ci(PGA) (THD + N)/S input capacitance of the PGA total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz at input signal of 1 kHz; PGA gain = 0 dB; note 4 Vi (0 dB) 1.0 V (RMS) Vi (-60 dB) S/N ct fs OL signal to noise ratio crosstalk between channels sample frequency (128fs) digital output level PGA gain = 0 dB, Vi = 1 V (RMS) Vi = 0.0 V PGA gain = 0 dB - - - - 90 - 0.640 - - -85 0.0056 -30 3.2 95 100 - -2.0 -80 0.01 -20 10.0 - - 7.04 - dB % dB % dBA dB MHz dBFS 1999 May 10 42 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 SYMBOL Filter stream DAC RES Vo(FS)(rms) SVRR Vo ct (THD + N)/S resolution PARAMETER CONDITIONS MIN. - TYP. - - - - - MAX. UNIT 16 VDD = 3.3 V fripple = 1 kHz Vripple(p-p) = 0.1 V maximum volume RL = 5 k fs = 44.1 kHz; RL = 5 k; note 5 at input signal of - 1 kHz (0 dB) - at input signal of - 1 kHz (-60 dB) - - - - - bits V dB dB dB full-scale output voltage (RMS value) supply voltage ripple rejection at VDDA and VDDO channel unbalance crosstalk between channels total harmonic distortion plus noise-to-signal ratio 0.66 60 0.03 95 -90 0.0032 -30 3.2 95 -80 0.01 -20 10 - dB % dB % dB S/N Notes signal-to-noise ratio at bipolar zero A-weighting at code 0000H 90 1. Strongly depends on the external decoupling capacitor connected to Vref(DA). 2. Cref in F. 3. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping. 4. Measured with the APLL as ADC clock source. 5. Measured with I2S-bus input as digital source. 1999 May 10 43 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC APPLICATION INFORMATION handbook, full pagewidth C34 47 F (16 V) C38 100 nF (63 V) VSSA1 39 +VA R35 1 C32 47 F (16 V) C21 100 nF (63 V) VDDA1 VSSA2 38 44 VDDA2 42 +VA R27 1 UDA1325 BCKI digital input playback WSI DI GP0/BCKI GP5/WSI GP1/DI 17 15 13 BCK digital input recording WS DA BCK WS DA 61 59 57 +VC X4 1 2 3 4 L1 1 2 3 4 8 7 6 5 VUSB R48 1.5 k R7 22 R16 D+ 22 D- 6 8 UDA1325H C15 10 nF (50 V) C16 10 nF (50 V) C18 22 pF (63 V) C17 22 pF (63 V) C8 analog input recording 47 F (16 V) C22 47 F (16 V) C44 10 nF (63 V) L5 1.5 H VINR 47 VINL 43 1 XTAL2b 26 C38 12 pF (63 V) X1 C37 12 pF (63 V) XTAL2a ADC XTAL C5 18 pF (50 V) L8 BLM32A07 L7 BLM32A07 L6 BLM32A07 C47 100 F (16 V) C46 100 F (16 V) C6 18 pF (50 V) 10 VSSI C25 100 nF (63 V) C24 100 nF (63 V) MGM760 48 MHz XTAL1b 25 XTAL1a 53 54 VA(ext) +VA +VC +VD C45 100 F (16 V) 9 VDDI 11 VSSE C26 100 nF (63 V) C27 100 nF (63 V) 12 VDDE VD(ext) L2 BLM32A07 L3 BLM32A07 GND R17 1 +VC R25 1 +VD Fig.8 Application diagram UDA1325H (continued in Fig.9). 1999 May 10 44 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 +V handbook, full pagewidthA C7 47 F (16 V) C19 100 nF (63 V) VSSA3 55 R10 1 C11 100 nF (63 V) +VA R8 1 VDDA3 VRN 52 49 VRP 51 56 58 60 62 64 3 5 7 50 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE D7 D6 D5 D4 D3 D2 D1 D0 LE OE 18 17 14 13 8 7 4 3 11 1 10 14 16 18 20 22 23 31 48 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 PSEN EA +VD R20 1 C36 100 nF (63 V) A0 A1 A2 VSS 21 19 40 41 SDA SCL Vref(DA) Vref(AD) C28 100 nF (63 V) C35 47 F (16 V) analog output playback C31 47 F (16 V) C29 100 nF (63 V) C41 47 F (16 V) 2 1 2 3 4 R28 4.7 k 8 VDD PTC SCL SDA R38 10 k R39 10 k 1 (I2C-bus) 3 +VD J3 2 1 (external ROM) +VD +VD 19 16 15 12 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC C24 GND +VD 100 nF (50 V) A0 A1 A2 A3 A4 A5 A6 A7 A8 10 9 8 7 6 5 4 3 25 11 12 13 15 16 17 18 19 O0 O1 O2 O3 O4 O5 O6 O7 D1 74HCT373D 9 6 5 2 20 D2 A9 24 EEPM27128 A10 A11 A12 A13 OE CE PGM VPP 21 23 2 26 22 20 27 1 14 28 VCC C25 GND +VD 100 nF (50 V) (internal ROM) UDA1325H D4 PCF85116-3 7 6 5 37 VOUTR 34 VOUTL C48 47 F (16 V) 2 1 63 GP4/BCKO GP3/WSO GP2/DO BCKO WSO DO digital output playback 36 35 4 33 VSSO C33 100 nF (63 V) C39 47 F (16 V) R43 1 +VA 32 VDDO 24 VSSX C28 100 nF (63 V) C18 100 nF (63 V) 28 RTCB TC SHTCB VDDX L13 BLM32A07 R26 1 +VC MGM761 Fig.9 Application diagram UDA1325H (continued from Fig.8). 1999 May 10 45 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... dbook, full pagewidth 1999 May 10 30 BCKI digital input playback WSI DI GP0/BCKI GP5/WSI GP1/DI 16 15 14 BCK digital input recording WS DA +VC X4 1 2 3 4 Philips Semiconductors Universal Serial Bus (USB) CODEC +VA C34 47 F (16 V) C38 100 nF (63 V) VSSA1 R35 1 C32 47 F (16 V) C21 100 nF (63 V) VDDA1 VSSA2 29 35 +VA R27 1 +VA C7 47 F (16 V) C19 100 nF (63 V) R10 1 C11 100 nF (63 V) +VA R8 1 +VD R20 1 VDDA2 33 VSSA3 42 VDDA3 VRN 39 37 VRP 38 C36 100 nF (63 V) A0 A1 A2 VSS 1 2 3 4 8 VDD D4 PCF85116-3 7 6 5 PTC SCL SDA +VD R38 10 k R39 10 k 1 (I2C-bus) 2 BCK WS DA 18 3 2 1 17 31 32 SDA SCL Vref(DA) Vref(AD) C28 100 nF (63 V) C31 47 F (16 V) C29 100 nF (63 V) C41 47 F (16 V) L1 1 2 3 4 8 7 6 5 VUSB R48 1.5 k R7 22 R16 D- 8 28 9 VOUTR C35 47 F (16 V) analog output playback D+ C15 10 nF (50 V) C16 10 nF (50 V) C18 22 pF (63 V) C17 22 pF (63 V) 22 UDA1325PS C8 analog input recording 47 F (16 V) C22 47 F (16 V) C44 10 nF (63 V) C38 12 pF (63 V) C37 12 pF (63 V) XTAL2a ADC XTAL C5 18 pF (50 V) C6 18 pF (50 V) XTAL1a 40 41 11 VSSI C25 100 nF (63 V) C24 100 nF (63 V) 10 VDDI 12 VSSE C26 100 nF (63 V) C27 100 nF (63 V) 13 VDDE 24 VSSO C33 100 nF (63 V) C39 47 F (16 V) R43 1 +VA 23 VDDO 19 VSSX C28 100 nF (63 V) C18 100 nF (63 V) 22 L5 1.5 H VINL 34 VINR 36 25 VOUTL C48 47 F (16 V) 46 6 5 GP4/BCKO GP3/WSO GP2/DO BCKO WSO DO 1 XTAL2b 4 21 digital output playback X1 48 MHz XTAL1b 27 20 26 7 RTCB TC SHTCB VDDX VA(ext) L8 BLM32A07 L7 BLM32A07 L6 BLM32A07 C47 100 F (16 V) C46 100 F (16 V) +VA +VC +VD C45 100 F (16 V) MGS271 Preliminary specification L2 BLM32A07 L3 BLM32A07 L13 BLM32A07 VD(ext) R26 1 +VC UDA1325 R17 1 +VC R25 1 +VD GND Fig.10 Application diagram UDA1325PS. Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC PACKAGE OUTLINES SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) UDA1325 SOT270-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 42 22 pin 1 index E 1 21 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 90-02-13 95-02-04 1999 May 10 47 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 52 33 32 ZE A e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L pin 1 index wM e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 1999 May 10 48 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1999 May 10 49 MANUAL SOLDERING UDA1325 Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC Suitability of IC packages for wave, reflow and dipping soldering methods UDA1325 SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount BGA, SQFP HLQFP, HSQFP, HSOP, HTSSOP, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. suitable(2) not suitable not not not suitable(3) recommended(4)(5) recommended(6) suitable REFLOW(1) - suitable suitable suitable suitable suitable - - - - - DIPPING suitable 1999 May 10 50 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values UDA1325 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 May 10 51 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999 Internet: http://www.semiconductors.philips.com SCA 64 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/750/01/pp52 Date of release: 1999 May 10 Document order number: 9397 750 02805 |
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